Verification status: The source article contains zero verifiable data points. It asks one question and then ends. I spent an afternoon trying to audit its claims. There were no claims. That absence is a signal. A binary question about a structurally divergent memory market is a false dichotomy. The answer is not 'top' or 'bottom.' The answer is 'which curve are you looking at?'
HBM3E, the fifth-generation high-bandwidth memory used in NVIDIA's flagship accelerators, is selling for five to eight times the price of equivalent-capacity DDR5. It is still allocation-controlled. Meanwhile, commodity DRAM and NAND are only halfway through a recovery from the 2023 downturn. Those are two different cycles living in the same market. Mixing them into one 'AI memory chip' category is like treating a DeFi protocol and a bank deposit as the same risk class. Code does not lie, only the documentation does. The labels in this debate are documentation.
The original piece is not a research report. It is a sentiment probe with no sources and no technical framework. Because the question itself is important, I will not review the article. I will audit the question. That means separating the variables that actually determine a memory cycle: process technology, yield, capacity conversion, buyer concentration, capital expenditure, valuation practice, and export controls. After that, the 'top or bottom' question does not resolve into a single answer. It resolves into a timeline.
Context: Why Memory Cycles Are Not Like Software Cycles
Memory is the most cyclical semiconductor category. It behaves more like a commodity with a nine-figure factory ticket than a technology product. When prices rise, manufacturers add capacity with an eighteen-to-thirty-month lag. When that capacity lands, prices collapse. Then manufacturers cut production and prices bottom. This rhythm has repeated every two to four years since DRAM became a product. The 2023 crash was not an exception. It was the textbook version: overcapacity, inventory glut, negative margins, and production cuts across SK hynix, Samsung, and Micron.
The AI era complicates that rhythm. HBM is not commodity DRAM. It is a vertically stacked, TSV-connected assembly of DRAM dies with an advanced logic base die. It requires TSV etching, temporary bonding, batch reflow molding, and, eventually, hybrid bonding. The process is closer to advanced packaging than to conventional memory fabrication. The supply constraint is not only DRAM wafers. It is also TSV capacity, test capacity, CoWoS 2.5D integration, and NVIDIA's qualification queue. That last item is the one most models miss.
This is why the source's single question fails. HBM and commodity memory are on different clocks. HBM is supply-constrained and price-rising. Commodity DRAM is recovering from a deep inventory correction. NAND is still digesting overcapacity. Those three charts will not peak at the same time. If it cannot be verified, it cannot be trusted, and the first thing to verify is which memory product the question is about.
Two Curves, Not One Cycle
The structural split can be stated plainly. AI server storage content has roughly doubled compared to traditional servers. AI servers carry 1.5 to 2 terabytes of DRAM and ten to thirty terabytes of NAND, compared to half a terabyte to one terabyte and four to eight terabytes in legacy servers. That is real demand, but it is concentrated in high-end products. HBM3E is a custom product built to order for AI accelerators. Commodity DDR4 and SATA SSDs are not. They do not share a price curve, a supply curve, or a demand curve.
One of the largest errors in the current debate is treating HBM as the entire memory market. HBM is the high-margin center of the AI story, but it is still a fraction of total bit shipments. The rest of memory is in a slower recovery. That means the market can show simultaneous strength and weakness. HBM contract prices can rise while spot DRAM prices stagnate. Cloud capex can grow while consumer demand stays flat. The binary framing collapses the moment you separate the two curves.
I saw the same error during the 2022 bear market. While stress-testing Aave V2 liquidation logic, I ran 150 crash scenarios and found that the failure point was almost never the collateral ratio. It was the oracle feed between market price and protocol action. Memory cycles have the same structure. The failure point is not the demand story. It is the feed between capital expenditure and shipped HBM. That feed runs through TSV lines, MR-MUF equipment, packaging capacity, and NVIDIA's qualification process.
Core: The Technical Variables That Determine the Top
The first constraint is yield. The second is capacity. The third is demand concentration. The fourth is financial valuation. Each one behaves differently, and each one has a different timeline.
Yield Is the Real Release Valve
The three major memory manufacturers are all ramping HBM3E yield. Industry consensus places HBM yield well below conventional DRAM yield. That is the bottleneck. If yield improves faster than expected, supply releases faster, and the 'top' arrives earlier. If yield improves slowly, the shortage extends into 2026. Most market commentary ignores yield because it is not visible in public filings. But it is the deterministic variable. I would rather track qualification announcements than price charts. Yield curves are the smart contract of the memory cycle. They execute the supply schedule, and code does not lie — only the published roadmap does.
Process technology also matters. Current HBM3E products are built on DRAM nodes around 1-alpha, 1-beta, and 1-gamma nanometer-class processes. NAND has moved beyond 200 layers of 3D stacking. DRAM still relies on the 1T1C cell structure, but HBM adds TSV vertical interconnects to stack multiple DRAM dies. The manufacturing complexity is closer to advanced packaging than to conventional memory. The gap between a memory design and a shipped HBM stack is filled with equipment that has long lead times. TSV etchers, bonders, and testers are the real capacity ceiling.
HBM4 is the next scheduled release, with mass production expected in the second half of 2025 or 2026. It will move to a 2048-bit interface and likely outsource the logic base die to an advanced foundry. That will increase I/O density and energy efficiency, but it also introduces a new set of process risks. Every generation change resets the yield curve. A slow HBM4 qualification could delay the next wave of supply and push the market's peak further out. The 'top' of this cycle is not a price level. It is an event on the yield roadmap.
Capacity: The Market Is Reallocating, Not Just Building
The second variable is capacity. The industry is spending heavily. SK hynix is expanding its M15X fab and Cheongju site with an estimated fifteen to twenty billion dollars to more than double HBM capacity. Samsung is ramping P4 and P5 in Pyeongtaek. Micron is building new fabs in Idaho and New York with more than fifty billion dollars in planned investment. Combined capital expenditure across the three manufacturers is roughly sixty to ninety billion dollars per year in 2024 and 2025.
But the new capacity that matters for the 2025 and 2026 supply picture is not greenfield. It is conversion. Existing DRAM fab capacity can be converted to HBM production within six to twelve months. That is much faster than building a new fab. The memory industry is not only printing new supply. It is reallocating existing supply away from commodity DRAM and into HBM. That has a hidden effect: it tightens commodity DRAM supply. So even if HBM prices peak, traditional DRAM prices could continue to recover. This is the structural divergence the source never mentions.
Capacity announcements are not supply. A fab announcement is more like a commitment in a smart contract. It becomes supply only when yield, packaging capacity, and customer qualification all pass. The history of memory cycles is a history of capital expenditure discipline failing. The top of the previous cycle was accompanied by aggressive expansion. The bottom came after expansion met demand destruction. The same script is now playing out in HBM. The only difference is that demand is anchored to a single customer. That makes the cycle faster and more fragile.
Demand Concentration: The Single-Point-of-Failure Risk
The demand side looks robust. Cloud hyperscalers — Microsoft, Google, Amazon, and Meta — guided more than two hundred billion dollars in combined capital expenditure for 2024, with 2025 guidance still rising. AI training GPU shipments are expected to exceed four million units in 2025, with each GPU requiring six to eight HBM3E stacks. That is a genuine demand pull. It is not a speculative inventory build. But there is a concentration problem.
NVIDIA accounts for an estimated 70 to 80 percent of HBM demand. That makes the entire HBM supply chain a single-customer market. If NVIDIA reduces order volume, changes its memory architecture, or shifts to a second supplier faster than expected, the memory manufacturers' revenue quality changes instantly. The market narrative treats NVIDIA as a growth engine. I treat it as a key-man risk. Security is a process, not a feature, and in this case, the process is multi-sourcing.
There is also a pricing transmission chain. HBM cost is roughly 10 to 20 percent of an AI accelerator's bill of materials, second only to the GPU die itself. If memory prices rise, NVIDIA can pass the cost to cloud customers. That protects NVIDIA's margin but does not protect the underlying demand. At some point, the cost of an AI server becomes a constraint on deployment. The market has not modeled that elasticity. It assumes demand is linear. It is not.
Valuation: The Wrong Measurement Tool
Financial media usually values memory stocks with price-to-earnings ratios. That is an error. Memory earnings are the most volatile earnings in the semiconductor industry. At cycle bottom, earnings are negative, so PE is meaningless. At cycle top, earnings are inflated, so PE looks artificially cheap. The correct instruments are price-to-book and price-to-sales.
The historical ranges are consistent. Memory cycle bottoms tend to show price-to-book below one. Cycle tops tend to show price-to-book above 2.5 to 3 times. In the 2024-2025 window, Samsung sits around 1.2 to 1.5 times book. SK hynix sits around 1.8 to 2.2 times. Micron sits around 2.0 to 2.5 times. Those are not bottom levels, but they are also not historical top levels. They are mid-cycle.
The same logic applies to return on equity. Memory bottom ROE is low single digits or negative. Top ROE can reach 20 to 30 percent. Current ROE is recovering but not at historical peak. That does not prove the market has further to run. It does prove the 'top' is not visible in the valuation inputs yet.
There is a nuance. Gross margin is approaching levels that historically correspond to late-cycle pricing. SK hynix and Samsung could recover memory gross margins to 30 to 40 percent in 2025. If that happens while PB is still below historical tops, the market is in an earnings-up, multiple-mid state. That is a classic mid-cycle position. The dangerous point comes when earnings are upgraded while PB crosses three times. That is when the consensus becomes an algorithm instead of a judgment. If the source article wants a simple answer, the valuation data says: not yet.
Competitive Landscape: Why SK hynix Leads and Samsung Lags
The market share structure is less stable than it appears. In total DRAM, Samsung leads with roughly 40 percent. But in HBM, SK hynix has more than 50 percent, Samsung has 35 to 40 percent, and Micron has 10 to 15 percent. The gap is not entirely technological. Samsung's HBM3 and HBM3E reportedly faced repeated qualification issues at NVIDIA, including thermal and power consumption problems. SK hynix established an early production relationship with NVIDIA and locked in qualification cycles. That relationship is the actual moat. The silicon advantage is real, but the certification advantage compounds.
This matters for the 'top' question because qualification cycles are slow. Once a design is validated, it is not easily replaced. HBM generation cycles are about 18 to 24 months. So a leadership position in one generation often carries into the next. SK hynix's lead is not a temporary arbitrage. It is a process advantage in both manufacturing and customer trust.
Chinese memory makers are the wildcard. CXMT is ramping DRAM and YMTC is ramping NAND. Neither has volume HBM production yet. Domestic HBM efforts exist, but TSV tooling, advanced packaging equipment, and material supply remain major bottlenecks. If export controls tighten, Chinese HBM development will slow. If Chinese HBM somehow reaches volume production by 2026 or 2027, it will not serve NVIDIA. It will serve the domestic AI chip ecosystem. That is not a threat to the current global HBM pricing structure in the near term. It is a geopolitical supply split that raises costs for everyone.
Geopolitics: The Double-Edged Export Control
The December 2024 US export control rule added HBM and HBM manufacturing equipment to the China restriction list. That was the first time HBM was explicitly controlled. The effects are asymmetric. On one hand, it denies Chinese AI accelerators access to the highest-bandwidth memory. On the other hand, it removes a large potential buyer from the global HBM market, increasing the concentration of the remaining buyer pool even further.
This is not a stable equilibrium. The restriction forces China into a domestic substitution path. It may also push CXMT to accelerate HBM development despite equipment constraints. That is the same dynamic I saw during my institutional custody review in 2024, when a multi-signature wallet configuration had to be translated into audit-ready documentation for compliance teams. Technical restrictions do not remove risk. They move it to a new layer. The compliance layer is part of the architecture, not an afterthought.
If the entire HBM supply chain is dependent on a single customer today, export controls strengthen that dependency. NVIDIA becomes not only the largest buyer but effectively the only buyer at scale. That concentration is the hidden structural risk behind the 'shortage' narrative. If it cannot be verified, it cannot be trusted, and the one variable every forecast should verify is the buyer concentration chart.
Contrarian Reading: The Narrative Peaked Before the Silicon
The source article is not a semiconductor analysis. It is a market sentiment artifact. When a blockchain and Web3 outlet publishes a speculative question about AI memory chips, it is not a sign that the industry has peaked. It is a sign that the memory cycle narrative has expanded beyond the semiconductor analyst community. I have seen this pattern before in both crypto and traditional markets. It typically appears in the middle of a cycle, not at the end. The late stage is marked by unanimity, not by confused binary polling.
The actual 'top' risk is supply-side, not demand-side. The 2025 H2 to 2026 capacity release window is the first real test. Total HBM production is projected to grow sharply in 2025. If AI demand continues at the current growth rate, the market absorbs it. If cloud capex guidance gets revised downward, the second half becomes a margin event. The market is not positioned for that. It is positioned for monotonic growth.
There is also a substitution risk that the article completely misses. CXL memory expansion is still early, but it could reduce the premium attached to HBM density in certain workloads. AI ASIC projects from Google, Amazon, and others are building custom memory hierarchies. They are not abandoning HBM, but they are reducing the monoculture. That is the slow-moving hedge. The market treats HBM as irreplaceable. In technology, 'irreplaceable' is a temporary state. I would not build a long-term thesis on that assumption.
A Monitoring Checklist for the Second Half
Because the source provides no framework, a useful replacement is a simple verification checklist. The first item is HBM4 qualification timing. If qualification slips, the next supply wave slips with it. The second item is NVIDIA's order revisions. A downward revision in volume is more important than any price index. The third item is TSV and advanced packaging capacity. The bottleneck is not just DRAM wafers. The fourth item is the price-to-book multiple of SK hynix and Micron. A move above 2.5 to 3 times book with peak earnings would be a late-cycle signal. The fifth item is commodity DRAM pricing. If commodity memory starts rising while HBM prices flatten, the market is rotating rather than peaking.
That checklist is not a prediction. It is a set of conditions that would change my judgment. In an audit, you do not trust the conclusion until you can trace it back to the inputs. The same rule applies to market analysis. The easiest way to avoid the 'top or bottom' trap is to refuse the question and ask for the underlying variables instead.
Takeaway: The Question Is Wrong
If the question is 'has AI memory peaked,' the answer is no. HBM remains supply-constrained, HBM4 is still a risk event, and cloud capex is still rising. If the question is 'should I buy here,' that is a different trade. The market has already priced in a strong 2025. The asymmetric opportunity is not in HBM pricing. It is in the divergence between HBM and commodity DRAM, and in the capacity-conversion variable that most models ignore.
The real marker to watch is not a price chart. It is the 2025 H2 qualification results for HBM4, the first revision in NVIDIA's order book, and the PB multiples of the three memory manufacturers. Any one of those can falsify the bullish thesis. Until then, the correct position is not 'top' or 'bottom.' It is structural separation. AI memory is in a mid-cycle supercycle within a cyclical industry. The critical question is not whether memory is peaking. It is whether the market's mental model is one curve or two.